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1 ? november 2, 2004 fn8183.0 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. xdcp is a trademark of intersil americas, inc. copy right intersil americas inc. 2004. all rights reserved all other trademarks mentioned are the property of their respective owners. x9317 low noise, low power, 100 taps digitally controlled potentiometer (xdcp?) the intersil x9317 is a digitally controlled potentiometer (xdcp). the device consists of a resistor array, wiper switches, a control section, and nonvolatile memory. the wiper position is controlled by a 3-wire interface. the potentiometer is implemen ted by a resistor array composed of 99 resistive elements and a wiper switching network. between each element and at either end are tap points accessible to the wiper terminal. the position of the wiper element is controlled by the cs , u/d , and inc inputs. the position of the wiper can be stored in nonvolatile memory and then be recalled upon a subsequent power-up operation. the device can be used as a three-terminal potentiometer for voltage control or as a two-terminal variable resistor for current control in a wide variety of applications. features ? solid-state potentiometer ? 3-wire serial up/down interface ? 100 wiper tap points - wiper position stored in nonvolatile memory and recalled on power-up ? 99 resistive elements - temperature compensated - end to end resistance range 20% ? low power cmos -v cc = 2.7v to 5.5v, and 5v 10% - standby current < 1a ? high reliability - endurance, 100,000 data changes per bit - register data retention, 100 years ?r total values = 1k ? , 10k ? , 50k ? , 100k ? ? packages - 8-lead soic, dip, tssop, and msop applications ? lcd bias control ? dc bias adjustment ? gain and offset trim ? laser diode bias control ? voltage regulator output control pinouts x9317 (8-ld tssop) top view x9317 (8-ld dip/soic/msop) top view inc r l /v l cs v cc 1 2 3 4 8 7 6 5 x9317 u/d r w /v w v ss r h /v h r h v cc inc u/d 1 2 3 4 8 7 6 5 x9317 v ss cs r l r w data sheet
2 fn8183.0 block diagram ordering information part number rtotal package temp range (c) x9317zs8 1k ? 8-lead soic 0 to 70 x9317zs8i 1k ? 8-lead soic -40 to +85 x9317zp 1k ? 8-lead plastic dip 0 to 70 x9317zv8 1k ? 8-lead tssop 0 to 70 x9317zv8i 1k ? 8-lead tssop -40 to +85 x9317zm8 1k ? 8-lead msop 0 to 70 x9317zm8i 1k ? 8-lead msop -40 to +85 x9317ws8 10k ? 8-lead soic 0 to 70 x9317ws8i 10k ? 8-lead soic -40 to +85 x9317wp 10k ? 8-lead plastic dip 0 to 70 x9317wpi 10k ? 8-lead plastic dip -40 to +85 x9317wv8 10k ? 8-lead tssop 0 to 70 x9317wv8i 10k ? 8-lead tssop -40 to +85 x9317wm8 10k ? 8-lead msop 0 to 70 x9317wm8i 10k ? 8-lead msop -40 to +85 x9317us 50k ? 8-lead soic 0 to 70 x9317us8 50k ? 8-lead soic 0 to 70 x9317us8i 50k ? 8-lead soic -40 to +85 x9317up 50k ? 8-lead plastic dip 0 to 70 x9317upi 50k ? 8-lead plastic dip -40 to +85 x9317uv8 50k ? 8-lead tssop 0 to 70 x9317uv8i 50k ? 8-lead tssop -40 to +85 x9317um8 50k ? 8-lead msop 0 to 70 x9317um8i 50k ? 8-lead msop -40 to +85 x9317ts8 100k ? 8-lead soic 0 to 70 x9317ts8i 100k ? 8-lead soic -40 to +85 x9317tp 100k ? 8-lead plastic dip 0 to 70 x9317tpi 100k ? 8-lead plastic dip -40 to +85 x9317tv8 100k ? 8-lead tssop 0 to 70 x9317tv8i 100k ? 8-lead tssop -40 to +85 x9317tm8 100k ? 8-lead msop 0 to 70 x9317tm8i 100k ? 8-lead msop -40 to +85 notes: 1. add ?-t1? or ?-t2? suffix for tape and reel. 2. add ?-2.7? for 2.7v to 5.5v v cc limits option. ordering information (continued) part number rtotal package temp range (c) up/down counter 7-bit nonvolatile memory store and recall control circuitry one of one decoder resistor array r h u/d inc cs wiper switches hundred v cc v ss r l r w control and memory up/down (u/d ) increment (inc ) device select (cs ) v cc (supply voltage) v ss (ground) r h r w r l general detailed 0 1 2 96 97 98 99 pin descriptions dip/soic symbol brief description 1inc increment . toggling inc while cs is low moves the wiper either up or down. 2u/d up/down . the u/d input controls the direction of the wiper movement. 3r h the high terminal is equivalent to one of the fixed terminals of a mechanical potentiometer. 4v ss ground. 5r w the wiper terminal is equivalent to the mov able terminal of a mechanical potentiometer. 6 r l the low terminal is equivalent to one of the fixed terminals of a mechanical potentiometer. 7cs chip select . the device is selected when the cs input is low, and de-selected when cs is high. 8v cc supply voltage. x9317
3 fn8183.0 absolute m aximum ratings junction temperature under bias. . . . . . . . . . . . . . .-65 c to +135 c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c voltage on cs , inc , u/d and v cc with respect to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . -1v to +7v r h , r w , r l to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+6v lead temperature (soldering 10 seconds) . . . . . . . . . . . . . . . . 300c i w (10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.8ma caution: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stres s rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not im plied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. potentiometer specifications v cc = full range, t a = full operating temperature range unless otherwise stated symbol parameter test conditions/notes min typ (note 4) max unit r total end to end resistance tolerance see ordering information for values -20 +20 % v rh / rl r h /r l terminal voltage v ss = 0v v ss v cc v power rating r total 10k ? 10 mw r total = 1k ? 25 mw r w wiper resistance i w = 1ma, v cc = 5v 200 400 ? i w = 1ma, v cc = 2.7v 400 1000 ? i w wiper current (note 5) see test circuit -4.4 +4.4 ma noise (note 7) ref: 1khz -120 dbv resolution 1% absolute linearity (note 1) v(rh) = v cc , v(rl) = 0v -1 +1 mi (note 3) relative linearity (note 2) -0.2 +0.2 mi (note 3) r total temperature coefficient (note 5) 300 ppm/c ratiometric temperature coefficient (notes 5, 6) -20 +20 ppm/c c h /c l /c w (note 5) potentiometer capacitances see equivalent circuit 10/10/25 pf v cc supply voltage x9317 4.5 5.5 v x9317-2.7 2.7 5.5 v dc electrical specifications v cc = 5v 10%, t a = full operating temperature range unless otherwise stated symbol parameter test conditions min typ (note 4) max unit i cc1 v cc active current (increment) cs = v il , u/d = v il or v ih and inc = v il /v ih @ min. t cyc r l , r h , r w not connected 50 a i cc2 v cc active current (store) (non-volatile write) cs = v ih , u/d = v il or v ih and inc = v il or v ih . r l , r h , r w not connected 400 a i sb standby supply current cs v ih , u/d and inc =v il r l , r h , r w not connected 1a i li cs , inc , u/d input leakage current v in = v ss to v cc -10 +10 a v ih cs , inc , u/d input high voltage v cc x 0.7 v cc + 0.5 v v il cs , inc , u/d input low voltage -0.5 v cc x 0.1 v x9317
4 fn8183.0 test circuit equivalent circuit c in (note 5) cs , inc , u/d input capacitance v cc = 5v, v in = v ss , t a = 25c, f = 1mhz 10 pf dc electrical specifications v cc = 5v 10%, t a = full operating temperature range unless otherwise stated (continued) symbol parameter test conditions min typ (note 4) max unit endurance and data retention v cc = 5v 10%, t a = full operating temperature range parameter min unit minimum endurance 100,000 data changes per bit data retention 100 years notes: 1. absolute linearity is utilized to determine ac tual wiper voltage versus expected voltage = [v(r w(n)(actual) )-v(r w(n)(expected) )]/mi v(r w(n)(expected) ) = n(v(r h )-v(r l ))/99 + v(r l ), with n from 0 to 99. 2. relative linearity is a measure of the error in step size between taps = [v(r w(n+1) )-(v(r w(n) ) - mi)]/mi. 3. 1 ml = minimum increment = [v(r h )-v(r l )]/99. 4. typical values are for t a = 25c and nominal supply voltage. 5. this parameter is not 100% tested. 6. ratiometric temperature coefficient = (v(r w ) t1(n) -v(r w ) t2(n) )/[v(r w ) t1(n) (t1-t2) x 10 6 ], with t1 & t2 being 2 temperatures, and n from 0 to 99. 7. measured with wiper at tap position 99, r l grounded, using test circuit. force current test point r w a.c. conditions of test input pulse levels 0v to 3v input rise and fall times 10ns input reference levels 1.5v c h c l r w 10pf 10pf r total c w 25pf r h r l ac electrical specifications v cc = 5v 10%, t a = full operating temperature range unless otherwise stated symbol parameter min typ (note 4) max unit t cl cs to inc setup 50 ns t ld (note 5) inc high to u/d change 100 ns t di (note 5) u/d to inc setup 1 s t ll inc low period 960 ns t lh inc high period 960 ns t lc inc inactive to cs inactive 1 s t cphs cs deselect time (store) 10 ms t cphns (note 5) cs deselect time (no store) 100 ns t iw inc to r w change 1 5 s x9317
5 fn8183.0 power up and down requirements the recommended power up sequence is to apply v cc /v ss first, then the potentiometer voltages. during power-up, the data sheet parameters for the dcp do not fully apply until 1 millisecond after v cc reaches its final value. the v cc ramp spec is always in effect. in order to prevent unwanted tap position changes, or an inadv ertent store, bring the cs and inc high before or concurrently with the v cc pin on powerup. a.c. timing typical performance characteristics t cyc inc cycle time 2 s t r , t f (note 5) inc input rise and fall time 500 s t pu (note 5) power up to wiper stable 5s t r v cc (note 5) v cc power-up rate 0.2 50 v/ms t wr store cycle 510ms ac electrical specifications v cc = 5v 10%, t a = full operating temperature range unless otherwise stated (continued) symbol parameter min typ (note 4) max unit cs inc u/d r w t ci t il t ih t cyc t id t di t iw mi (3) t ic t cphs t f t r 10% 90% 90% t cphns -55 -350 -300 -250 -200 -150 -100 -50 0 -45 -35 -25 -15 -5 5 15 25 35 temperature (c) ppm 45 55 65 75 85 95 105115125 figure 1. typical total resistance temperature coefficient x9317
6 fn8183.0 pin descriptions r h and r l the high (r h ) and low (r l ) terminals of the x9317 are equivalent to the fixed terminals of a mechanical potentiometer. the terminology of r l and r h references the relative position of the terminal in relation to wiper movement direction selected by the u/d input and not the voltage potential on the terminal. r w r w is the wiper terminal and is equivalent to the movable terminal of a mechanical potentiometer. the position of the wiper within the array is determined by the control inputs. the wiper terminal series resistance is typically 200 ? . up/down (u/d ) the u/d input controls the direction of the wiper movement and whether the counter is incremented or decremented. increment (inc ) the inc input is negative-edge triggered. toggling inc will move the wiper and either increment or decrement the counter in the direction indicated by the logic level on the u/d input. chip select (cs ) the device is selected when the cs input is low. the current counter value is stored in nonvolatile memory when cs is returned high while the inc input is also high. after the store operation is complete the x9317 will be placed in the low power standby mode until the device is selected once again. pin configuration principles of operation there are three sections of th e x9317: the control section, the nonvolatile memory, and the resistor array. the control section operates just like an up /down counter. the output of this counter is decoded to turn on a single electronic switch connecting a point on the resistor array to the wiper output. the contents of the counter ca n be stored in nonvolatile memory and retained for future use. the resistor array is comprised of 99 individual resistors connected in series. electronic switches at either end of the array and between each resistor provide an electrical connection to the wiper pin, r w . the wiper acts like its mechanical equivalent and does not move beyond the first or last position. that is, the counter does not wrap around when clocked to either extreme. the electronic switches on the device operate in a ?make before break? mode when the wiper changes tap positions. if the wiper is moved several positions, multiple taps are connected to the wiper for t iw (inc to v w change). the r total value for the device can temporarily be reduced by a significant amount if the wiper is moved several positions. when the device is powered-down, the last wiper position stored will be maintained in the nonvolatile memory. when power is restored, the contents of the memory are recalled and the wiper is set to the value last stored. instructions and programming the inc , u/d and cs inputs control the movement of the wiper along the resistor array. with cs set low the device is selected and enabled to respond to the u/d and inc inputs. high to low transitions on inc will increment or decrement (depending on the state of the u/d input) a seven bit counter. the output of this counter is decoded to select one of one hundred wiper positions along the resistive array. the value of the counter is stored in nonvolatile memory whenever cs transitions high while the inc input is also high. r h v cc inc u/d 1 2 3 4 8 7 6 5 x9317 dip/soic/msop v ss cs r l r w inc r l /v l cs v cc 1 2 3 4 8 7 6 5 x9317 tssop u/d r w /v w v ss r h /v h pin names symbol description r h high terminal r w wiper terminal r l low terminal v ss ground v cc supply voltage u/d up/down control input inc increment control input cs chip select control input x9317
7 fn8183.0 the system may select the x9317, move the wiper and deselect the device without havi ng to store the latest wiper position in nonvolatile memory. after the wiper movement is performed as described above and once the new position is reached, the system must keep inc low while taking cs high. the new wiper position will be maintained until changed by the system or until a powerup/down cycle recalled the previously stored data. this procedure allo ws the system to always power-up to a preset value stored in nonvolatile memory; then during system operation minor adjustments could be made. the adjustments might be based on user preference, system parameter changes due to temperature drift, etc. the state of u/d may be changed while cs remains low. this allows the host system to enable the device and then move the wiper up and down until the proper trim is attained. mode selection cs inc u/d mode l h wiper up l l wiper down h x store wiper position to nonvolatile memory h x x standby l x no store, return to standby l h wiper up (not recommended) l l wiper down (not recommended) x9317
8 fn8183.0 applications information electronic digitally controlled (xdcp) potentiometers provide three powerful application advan tages; (1) the variability and reliability of a solid-state potent iometer, (2) the flexibility of computer-based digital controls, and (3) the retentivity of nonvolatile memory used fo r the storage of multiple potentiometer settings or data. basic configurations of electronic potentiometers basic circuits v ref r w v ref i three terminal potentiometer; variable voltage divider two terminal variable resistor; variable current r h r l cascading techniques buffered reference voltage - + +5v r 1 +v v ref v out lmc7101 r w r w +v +v +v x (a) (b) v out = v w /r w single supply inverting amplifier voltage regulator r 1 r 2 i adj v o (reg) = 1.25v (1+r 2 /r 1 )+i adj r 2 v o (reg) v in 317 offset voltage adjustment + - v s v o r 2 r 1 100k ? 10k ? 10k ? 10k ? +5v lmc7101 comparator with hysteresis v ul = {r 1 /(r 1 +r 2 )} v o (max) v ll = {r 1 /(r 1 +r 2 )} v o (min) + - r 1 v o lmc7101 + - v s v o r 2 r 1 } lt311a (for additional circuits see an115) +5v r 2 +5v 100k 100k +5v v s v o = (r2/r1)v s r w } x9317
9 fn8183.0 packaging information note: 1. all dimensions in inches (in parentheses in millimeters) 2. package dimensions exclude molding flash 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) ref. pin 1 index 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) pin 1 seating 0.065 (1.65) 0.045 (1.14) 0.260 (6.60) 0.240 (6.10) 0.060 (1.52) 0.020 (0.51) typ. 0.010 (0.25) 0 15 8-lead plastic dual in-line (dip) package type p half shoulder width on all end pins optional .073 (1.84) max. 0.325 (8.25) 0.300 (7.62) plane x9317
10 fn8183.0 packaging information 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) pin 1 pin 1 index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0 - 8 x 45 8-lead plastic small outline gull wing package type s (soic) note: all dimensions in inches (in parentheses in millimeters) 0.250" 0.050"typical 0.050" typical 0.030" typical 8 places footprint x9317
11 fn8183.0 packaging information note: all dimensions in inches (in parentheses in millimeters) 8-lead plastic, tsso p, package type v see detail ?a? .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .114 (2.9) .122 (3.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0 - 8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x) (4.16) (7.72) (1.78) (0.42) (0.65) all measurements are typical x9317
12 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8183.0 packaging information 0.118 0.002 (3.00 0.05) 0.040 0.002 (1.02 0.05) 0.150 (3.81) ref. 0.193 (4.90) 0.030 (0.76) 0.036 (0.91) 0.032 (0.81) 0.007 (0.18) 0.005 (0.13) 0.008 (0.20) 0.004 (0.10) 0.0216 (0.55) 7 typ. r 0.014 (0.36) 0.118 0.002 (3.00 0.05) 0.012 + 0.006 / -0.002 (0.30 + 0.15 / -0.05) 0.0256 (0.65) typ. m package note: 1. all dimensions in inches and (millimeters) 0.220" 0.0256" typical 0.025" typical 0.020" typical 8 places footprint ref. 8-lead miniature small outline gull wing package type msop x9317
x9317 printer friendly version digitally controlled potentiometer (xdcp?) datasheets, related docs & simulations description key features parametric data related devices ordering information part no. design-in status temp. package msl price us $ x9317tm8 active comm 8 ld msop 1 2.30 x9317tm8-2.7 active comm 8 ld msop 1 2.54 x9317tm8-2.7t1 active comm 8 ld msop t+r 1 2.54 x9317tm8-2.7t2 active comm 8 ld msop t+r 1 2.54 x9317tm8i active ind 8 ld msop 1 2.87 x9317tm8i-2.7 active ind 8 ld msop 1 3.17 x9317tm8i-2.7t1 active ind 8 ld msop t+r 1 3.17 x9317tm8i-2.7t2 active ind 8 ld msop t+r 1 3.17 x9317tm8it1 active ind 8 ld msop t+r 1 2.87 x9317tm8it2 active ind 8 ld msop t+r 1 2.87 x9317tm8iz active ind 8 ld msop 2 2.87 x9317tm8iz-2.7 active ind 8 ld msop 2 3.17 x9317tm8iz-2.7t1 active ind 8 ld msop t+r 2 3.17 x9317tm8izt1 active ind 8 ld msop t+r 2 2.30 x9317tm8t1 active comm 8 ld msop t+r 1 2.30 x9317tm8t2 active comm 8 ld msop t+r 1 2.30 x9317tm8z active comm 8 ld msop 2 2.30 x9317tm8z-2.7 active comm 8 ld msop 2 2.54 x9317tm8z-2.7t1 active comm 8 ld msop t+r 2 2.54 x9317tm8zt1 active comm 8 ld msop t+r 2 2.30 x9317tp active comm 8 ld pdip n/a 1.96 x9317tp-2.7 active comm 8 ld pdip n/a 2.15 x9317tpi active ind 8 ld pdip n/a 2.44 x9317tpi-2.7 active ind 8 ld pdip n/a 2.68 x9317ts8 active comm 8 ld soic 1 1.96 x9317ts8-2.7 active comm 8 ld soic 1 2.15 x9317ts8-2.7t1 active comm 8 ld soic t+r 1 2.15 x9317ts8-2.7t2 active comm 8 ld soic t+r 1 2.15 x9317ts8i active ind 8 ld soic 1 2.44 x9317ts8i-2.7 active ind 8 ld soic 1 2.68 x9317ts8i-2.7t1 active ind 8 ld soic t+r 1 2.68 x9317ts8i-2.7t2 active ind 8 ld soic t+r 1 2.68 x9317ts8iz active ind 8 ld soic 1 2.44
x9317ts8iz-2.7 active ind 8 ld soic 1 2.68 x9317ts8iz-2.7t1 active ind 8 ld soic t+r 1 2.68 x9317ts8z active comm 8 ld soic 1 1.96 x9317ts8z-2.7 active comm 8 ld soic 1 2.15 x9317ts8z-2.7t1 active comm 8 ld soic t+r 1 2.15 x9317tv8 active comm 8 ld tssop 1 2.30 x9317tv8-2.7 active comm 8 ld tssop 1 2.54 x9317tv8-2.7t1 active comm 8 ld tssop t+r 1 2.54 x9317tv8-2.7t2 active comm 8 ld tssop t+r 1 2.54 x9317tv8i active ind 8 ld tssop 1 2.87 x9317tv8i-2.7 active ind 8 ld tssop 1 3.17 x9317tv8i-2.7t1 active ind 8 ld tssop t+r 1 3.17 x9317tv8i-2.7t2 active ind 8 ld tssop t+r 1 3.17 x9317tv8it1 active ind 8 ld tssop t+r 1 2.87 x9317tv8it2 active ind 8 ld tssop t+r 1 2.87 x9317tv8iz active ind 8 ld tssop 1 2.87 x9317tv8iz-2.7 active ind 8 ld tssop 1 3.17 x9317tv8iz-2.7t1 active ind 8 ld tssop t+r 1 3.17 x9317tv8izt1 active ind 8 ld tssop t+r 1 2.87 x9317tv8t1 active comm 8 ld tssop t+r 1 2.30 x9317tv8t2 active comm 8 ld tssop t+r 1 2.30 x9317tv8z active comm 8 ld tssop 1 2.30 x9317tv8z-2.7 active comm 8 ld tssop 1 2.54 x9317tv8z-2.7t1 active comm 8 ld tssop t+r 1 2.54 x9317tv8zt1 active comm 8 ld tssop t+r 1 2.30 x9317um8 active comm 8 ld msop 1 2.30 x9317um8-2.7 active comm 8 ld msop 1 2.54 x9317um8-2.7t1 active comm 8 ld msop t+r 1 2.54 x9317um8i active ind 8 ld msop 1 2.87 x9317um8i-2.7 active ind 8 ld msop 1 3.17 x9317um8i-2.7c7898 active ind 8 ld msop 1 x9317um8i-2.7t1 active ind 8 ld msop t+r 1 3.17 x9317um8i-2.7t2 active ind 8 ld msop t+r 1 3.17 x9317um8it1 active ind 8 ld msop t+r 1 2.87 x9317um8iz active ind 8 ld msop 2 2.87 x9317um8iz-2.7 active ind 8 ld msop 2 3.17 x9317um8iz-2.7t1 active ind 8 ld msop t+r 2 3.17 x9317um8izt1 active ind 8 ld msop t+r 2 2.87 x9317um8t1 active comm 8 ld msop t+r 1 2.30 x9317um8z active comm 8 ld msop 2 2.30 x9317um8z-2.7 active comm 8 ld msop 2 2.54 x9317um8z-2.7t1 active comm 8 ld msop t+r 2 2.54
x9317um8zt1 active comm 8 ld msop t+r 2 2.30 x9317up active comm 8 ld pdip n/a 1.96 x9317up-2.7 active comm 8 ld pdip n/a 2.15 x9317upi active ind 8 ld pdip n/a 2.44 x9317upi-2.7 active ind 8 ld pdip n/a 2.68 x9317us8 active comm 8 ld soic 1 1.96 x9317us8-2.7 active comm 8 ld soic 1 2.15 x9317us8-2.7t1 active comm 8 ld soic t+r 1 2.15 x9317us8c1039 active comm 8 ld soic 1 x9317us8c7898 active comm 8 ld soic 1 x9317us8i active ind 8 ld soic 1 2.44 x9317us8i-2.7 active ind 8 ld soic 1 2.68 x9317us8i-2.7t1 active ind 8 ld soic t+r 1 2.68 x9317us8i-2.7t2 active ind 8 ld soic t+r 1 2.68 x9317us8it1 active ind 8 ld soic t+r 1 2.44 x9317us8iz active ind 8 ld soic 1 2.44 x9317us8iz-2.7 active ind 8 ld soic 1 2.68 x9317us8iz-2.7t1 active ind 8 ld soic t+r 1 2.68 x9317us8izt1 active ind 8 ld soic t+r 1 2.44 x9317us8t1 active comm 8 ld soic t+r 1 1.96 x9317us8z active comm 8 ld soic 1 1.96 x9317us8z-2.7 active comm 8 ld soic 1 2.15 x9317us8z-2.7t1 active comm 8 ld soic t+r 1 2.15 x9317us8zt1 active comm 8 ld soic t+r 1 1.96 x9317uv8 active comm 8 ld tssop 1 2.30 x9317uv8-2.7 active comm 8 ld tssop 1 2.54 x9317uv8-2.7t1 active comm 8 ld tssop t+r 1 2.54 x9317uv8c7898 active comm 8 ld tssop 1 x9317uv8i active ind 8 ld tssop 1 2.87 x9317uv8i-2.7 active ind 8 ld tssop 1 3.17 x9317uv8i-2.7c7898 active ind 8 ld tssop 1 x9317uv8i-2.7t1 active ind 8 ld tssop t+r 1 3.17 x9317uv8i-2.7t2 active ind 8 ld tssop t+r 1 3.17 x9317uv8ic7898 active ind 8 ld tssop 1 x9317uv8it1 active ind 8 ld tssop t+r 1 2.87 x9317uv8iz active ind 8 ld tssop 1 2.87 x9317uv8iz-2.7 active ind 8 ld tssop 1 3.17 x9317uv8iz-2.7t1 active ind 8 ld tssop t+r 1 3.17 x9317uv8izt1 active ind 8 ld tssop t+r 1 2.87 x9317uv8t1 active comm 8 ld tssop t+r 1 2.30 x9317uv8z active comm 8 ld tssop 1 2.30 x9317uv8z-2.7 active comm 8 ld tssop 1 2.54 x9317uv8z-2.7t1 active comm 8 ld tssop t+r 1 2.54
x9317uv8zt1 active comm 8 ld tssop t+r 1 2.30 x9317wm8 active comm 8 ld msop 1 2.30 x9317wm8-2.7 active comm 8 ld msop 1 2.54 x9317wm8-2.7t1 active comm 8 ld msop t+r 1 2.54 x9317wm8i active ind 8 ld msop 1 2.87 x9317wm8i-2.7 active ind 8 ld msop 1 3.17 x9317wm8i-2.7t1 active ind 8 ld msop t+r 1 3.17 x9317wm8it1 active ind 8 ld msop t+r 1 2.87 x9317wm8iz active ind 8 ld msop 2 2.87 x9317wm8iz-2.7 active ind 8 ld msop 2 3.17 x9317wm8iz-2.7t1 active ind 8 ld msop t+r 2 3.17 x9317wm8izt1 active ind 8 ld msop t+r 2 2.87 x9317wm8t1 active comm 8 ld msop t+r 1 2.30 x9317wm8z active comm 8 ld msop 2 2.30 x9317wm8z-2.7 active comm 8 ld msop 2 2.54 x9317wm8z-2.7t1 active comm 8 ld msop t+r 2 2.54 x9317wm8zt1 active comm 8 ld msop t+r 2 2.30 x9317wp active comm 8 ld pdip n/a 1.96 x9317wp-2.7 active comm 8 ld pdip n/a 2.15 x9317wpi active ind 8 ld pdip n/a 2.44 x9317wpi-2.7 active ind 8 ld pdip n/a 2.68 x9317ws8 active comm 8 ld soic 1 1.96 x9317ws8-2.7 active comm 8 ld soic 1 2.15 x9317ws8-2.7t1 active comm 8 ld soic t+r 1 2.15 x9317ws8c7898 active comm 8 ld soic 1 x9317ws8i active ind 8 ld soic 1 2.44 x9317ws8i-2.7 active ind 8 ld soic 1 2.68 x9317ws8i-2.7c7898 active ind 8 ld soic 1 x9317ws8i-2.7c7923 active ind 8 ld soic 1 x9317ws8i-2.7t1 active ind 8 ld soic t+r 1 2.68 x9317ws8i-2.7t1c7898 active ind 8 ld soic 1 x9317ws8i-2.7t2 active ind 8 ld soic t+r 1 2.68 x9317ws8i-2.7t2c7898 active ind 8 ld soic t+r 1 x9317ws8ic7898 active ind 8 ld soic 1 x9317ws8it1 active ind 8 ld soic t+r 1 2.44 x9317ws8it1c7975 active ind 8 ld soic 1 x9317ws8iz active ind 8 ld soic 1 2.44 x9317ws8iz-2.7 active ind 8 ld soic 1 2.68 x9317ws8iz-2.7t1 active ind 8 ld soic t+r 1 2.68 x9317ws8izt1 active ind 8 ld soic t+r 1 2.44 x9317ws8t1 active comm 8 ld soic t+r 1 1.96 x9317ws8z active comm 8 ld soic 1 1.96 x9317ws8z-2.7 active comm 8 ld soic 1 2.15
x9317ws8z-2.7t1 active comm 8 ld soic t+r 1 2.15 x9317ws8zt1 active comm 8 ld soic t+r 1 1.96 x9317wv8 active comm 8 ld tssop 1 2.30 x9317wv8-2.7 active comm 8 ld tssop 1 2.54 x9317wv8-2.7t1 active comm 8 ld tssop t+r 1 2.54 x9317wv8c7898 active comm 8 ld tssop 1 x9317wv8i active ind 8 ld tssop 1 2.87 x9317wv8i-2.7 active ind 8 ld tssop 1 3.17 x9317wv8i-2.7c7898 active ind 8 ld tssop 1 x9317wv8i-2.7c7938 active ind 8 ld tssop 1 x9317wv8i-2.7t1 active ind 8 ld tssop t+r 1 3.17 x9317wv8i-2.7t1c7898 active ind 8 ld tssop 1 x9317wv8i-2.7t1c7938 active ind 8 ld tssop 1 x9317wv8i-2.7t2 active ind 8 ld tssop t+r 1 3.17 x9317wv8i-2.7t2c7898 active ind 8 ld tssop 1 x9317wv8i-2.7t3c7517 active ind 8 ld tssop 3 x9317wv8ic7898 active ind 8 ld tssop 1 x9317wv8it1 active ind 8 ld tssop t+r 1 2.87 x9317wv8iz active ind 8 ld tssop 1 2.87 x9317wv8iz-2.7 active ind 8 ld tssop 1 3.17 x9317wv8iz-2.7t1 active ind 8 ld tssop t+r 1 3.17 x9317wv8izt1 active ind 8 ld tssop t+r 1 2.87 x9317wv8t1 active comm 8 ld tssop t+r 1 2.30 x9317wv8t2 active comm 8 ld tssop t+r 1 2.30 x9317wv8z active comm 8 ld tssop 1 2.30 x9317wv8z-2.7 active comm 8 ld tssop 1 2.54 x9317wv8z-2.7t1 active comm 8 ld tssop t+r 1 2.54 x9317wv8zt1 active comm 8 ld tssop t+r 1 2.30 x9317zm8 active comm 8 ld msop 1 2.30 x9317zm8-2.7 active comm 8 ld msop 1 2.54 x9317zm8-2.7c7898 active comm 8 ld msop 1 x9317zm8-2.7t1 active comm 8 ld msop t+r 1 2.54 x9317zm8i active ind 8 ld msop 1 2.87 x9317zm8i-2.7 active ind 8 ld msop 1 3.17 x9317zm8i-2.7c7898 active ind 8 ld msop 1 x9317zm8i-2.7t1 active ind 8 ld msop t+r 1 3.17 x9317zm8it1 active ind 8 ld msop t+r 1 2.87 x9317zm8iz active ind 8 ld msop 2 2.87 x9317zm8iz-2.7 active ind 8 ld msop 2 3.17 x9317zm8iz-2.7t1 active ind 8 ld msop t+r 2 3.17 x9317zm8izt1 active ind 8 ld msop t+r 2 2.87 x9317zm8t1 active comm 8 ld msop t+r 1 2.30 x9317zm8z active comm 8 ld msop 2 2.30
x9317zm8z-2.7 active comm 8 ld msop 2 2.54 x9317zm8z-2.7t1 active comm 8 ld msop t+r 2 2.54 x9317zm8zt1 active comm 8 ld msop t+r 2 2.30 x9317zp active comm 8 ld pdip n/a 1.96 x9317zs8 active comm 8 ld soic 1 1.96 x9317zs8-2.7 active comm 8 ld soic 1 2.15 x9317zs8-2.7t1 active comm 8 ld soic t+r 1 2.15 x9317zs8i active ind 8 ld soic 1 2.44 x9317zs8i-2.7 active ind 8 ld soic 1 2.68 x9317zs8i-2.7t1 active ind 8 ld soic t+r 1 2.68 x9317zs8it1 active ind 8 ld soic t+r 1 2.44 x9317zs8iz active ind 8 ld soic 1 2.44 x9317zs8iz-2.7 active ind 8 ld soic 1 2.68 x9317zs8iz-2.7t1 active ind 8 ld soic t+r 1 2.68 x9317zs8izt1 active ind 8 ld soic t+r 1 2.44 x9317zs8t1 active comm 8 ld soic t+r 1 1.96 x9317zs8z active comm 8 ld soic 1 1.96 x9317zs8z-2.7 active comm 8 ld soic 1 2.15 x9317zs8z-2.7t1 active comm 8 ld soic t+r 1 2.15 x9317zs8zt1 active comm 8 ld soic t+r 1 1.96 x9317zv8 active comm 8 ld tssop 1 2.30 x9317zv8-2.7 active comm 8 ld tssop 1 2.54 x9317zv8-2.7t1 active comm 8 ld tssop t+r 1 2.54 x9317zv8i active ind 8 ld tssop 1 2.87 x9317zv8i-2.7 active ind 8 ld tssop 1 3.17 x9317zv8i-2.7c7898 active ind 8 ld tssop 1 x9317zv8i-2.7t1 active ind 8 ld tssop t+r 1 3.17 x9317zv8i-2.7t1c7898 active ind 8 ld tssop 1 x9317zv8i-2.7t2 active ind 8 ld tssop t+r 1 3.17 x9317zv8i-2.7t2c7898 active ind 8 ld tssop 1 x9317zv8it1 active ind 8 ld tssop t+r 1 2.87 x9317zv8iz active ind 8 ld tssop 1 2.87 x9317zv8iz-2.7 active ind 8 ld tssop 1 3.17 x9317zv8iz-2.7t1 active ind 8 ld tssop t+r 1 3.17 x9317zv8izt1 active ind 8 ld tssop t+r 1 2.87 x9317zv8t1 active comm 8 ld tssop t+r 1 2.30 x9317zv8z active comm 8 ld tssop 1 2.30 x9317zv8z-2.7 active comm 8 ld tssop 1 2.54 x9317zv8z-2.7t1 active comm 8 ld tssop t+r 1 2.54 x9317zv8zt1 active comm 8 ld tssop t+r 1 2.30 xlabview01 active n/a 91.77 xlabview01z active eval board n/a 91.77
x9317uv8iz-2.7t2 coming soon ind 8 ld tssop t+r 1 x9317uv8t2 coming soon comm 8 ld tssop 1 x9317ws8iz-2.7t2 coming soon ind 8 ld soic t+r 1 x9317wv8zt2 coming soon comm 8 ld tssop t+r 1 x9317tm8iz-2.7t2 inactive ind 8 ld msop t+r 2 x9317tm8izt2 inactive ind 8 ld msop t+r 2 x9317tm8z-2.7t2 inactive comm 8 ld msop t+r 2 x9317tm8zt2 inactive comm 8 ld msop t+r 2 x9317ts8iz-2.7t2 inactive ind 8 ld soic t+r x9317ts8z-2.7t2 inactive comm 8 ld soic t+r x9317tv8iz-2.7t2 inactive ind 8 ld tssop t+r x9317tv8izt2 inactive ind 8 ld tssop t+r x9317tv8z-2.7t2 inactive comm 8 ld tssop t+r x9317tv8zt2 inactive comm 8 ld tssop t+r x9317um8iz-2.7t2 inactive ind 8 ld msop t+r 2 x9317us inactive comm 8 ld soic 1 x9317us8iz-2.7t2 inactive ind 8 ld soic t+r x9317wv8iz-2.7t2 inactive ind 8 ld tssop t+r x9317zv8iz-2.7t2 inactive ind 8 ld tssop t+r 3.17 the price listed is the manufacturer's suggested retail price for quantities between 100 and 999 units. however, prices in today's market are fluid and may change without notice. msl = moisture sensitivity level - per ipc/jedec j-std-020 smd = standard microcircuit drawing description the intersil x9317 is a digitally controlled potentiometer (xdcp). the device consists of a resistor array, wiper switches, a control section, and nonvolatile memory. the wiper position is controlled by a 3-wire interface. the potentiometer is implemented by a resistor array composed of 99 resistive elements and a wiper switching network. between each element and at either end are tap points accessible to the wiper terminal. the position of the wiper element is controlled by the cs , u/ d , and inc inputs. the position of the wiper can be stored in nonvolatile memory and then be recalled upon a subsequent power-up operation. the device can be used as a three-terminal potentiometer for voltage control or as a two-terminal variable resistor for current control in a wide variety of applications. key f eatures solid-state potentiometer 3-wire serial up/down interface 100 wiper tap points wiper position stored in nonvolatile memory and recalled on power-up 99 resistive elements temperature compensated end to end resistance range 20% low power cmos v cc = 2.7v to 5.5v, and 5v 10% standby current < 1a high reliability endurance, 100,000 data changes per bit register data retention, 100 years rtotal values = 1k , 10k , 50k , 100k packages
8 ld soic, dip, tssop, and msop pb-free plus anneal available (rohs compliant) related documentation application note(s): a compendium of application circuits for intersil?s digitally-controlled (xdcp) potentiometers a primer on digitally-controlled potentiometers application of intersil digitally controlled potentiometers (xdcp?) as hybrid analog/digital feedback system control elements dc/dc module trim with digital potentiometers designing power supplies using intersil?s xdcp mixed signal products power supply and dc to dc converter control using intersil digitally controlled potentiontiometers (xdcps) putting analog on the bus shaft encoder drives multiple intersil digitally controlled potentiontiometers (xdcps) tone, balance, and volume control using a quad xdcp working with the intersil 3-wire dcp devices datasheet(s): low noise, low power, 100 taps digitally controlled potentiometer (xdcp?) technical brief(s): converting a fixed pwm to an adjustable pwm evaluation board(s): intersil_xdcp_test_utility_manual_rev_3.2.3.pdf labview_xdcp_software.zip labview_xdcp_upgrade_3.2.3.zip readme_xicorlabview_v3.2.3.txt xdcp_vref evaluation board kit documentation and software accesshw.zip technical homepage: digitally controlled potentiometers (dcps) and capacitors (dccs) precision analog homepage parametric data number of dcps single number of taps 100 memory type non-volatile bus interface type 3-wire (up/down) resistance options (k ) 1, 10, 50, 100 v cc range (v) 2.7 to 5.5 dcp differential terminal voltage (v) 0 to +5.5 terminal voltage range v l to v h (v) 0 to v cc resistance taper linear wiper current (ma) 1 wiper resistance ( ) 200 standby current i sb ( a) 1 applications lcd bias control dc bias adjustment gain and offset trim laser diode bias control voltage regulator output control related devices parametric table
x9318 digitally controlled potentiometer (xdcp?) x9319 digitally controlled potentiometer (xdcp?) x9c102 digitally controlled potentiometer (xdcp?) x9c103 digitally controlled potentiometer (xdcp?) x9c104 digitally controlled potentiometer (xdcp?) x9c303 logarithmic digitally controlled potentiometer (xdcp?), terminal voltage 5v, 100 taps, log taper x9c503 digitally controlled potentiometer (xdcp?) about us | careers | contact us | investors | legal | privacy | site map | subscribe | intranet ?2007. all rights reserved.

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